1. Field of the Invention
The invention relates to memories, and more particularly to reading data from memories.
2. Description of the Related Art
A memory comprises a plurality of storage units for storing data. For example, a flash memory comprises a plurality of blocks, and each of the blocks comprises a plurality of pages. The pages and the blocks are storage units of the flash memory. When a memory receives a write command from a controller, the memory stores data to storage units thereof according to the write command. When a memory receives a read command from a controller, the memory reads data from storage units thereof according to the read command, and then sends the data back to the controller. A memory generally reads data with a sense amplifier. A first terminal of the sense amplifier is coupled to a sense voltage, and a second terminal of the sense amplifier is coupled to an output terminal of a storage unit to be read. When the storage unit to be read outputs data to the output terminal, the sense amplifier compares the voltage on the output terminal of the storage unit with the sense voltage to determine whether the output data has a bit value of 0 or 1. The memory then sends the bit value of the output data to the controller, thus completing the data read operation.
When a plurality of storage units of a memory is read, the storage units storing the same data may output different voltages. For example, a storage unit with a location near a voltage source may output a higher voltage, and a storage unit with a location far from the voltage source may output a lower voltage. In addition, a storage unit may output different voltages when neighboring storage units store different data values. When a sense amplifier of a memory determines bit values of a plurality of storage units according to the same sense voltage, some of the bit values of the storage units may be wrongly identified, leading to read process errors.
Referring to FIG. 1A, a schematic diagram of probability distribution of an output voltage of a normal memory cell of a multi-level cell (MLC) memory is shown. Assume that the normal memory cell of the MLC memory can output four voltage levels, each voltage level corresponds to one of four storage bit combination 00, 01, 10, and 11, and the probability distributions of the four voltage levels are respectively marked as 101, 102, 103, and 104. The memory compares an output voltage of a memory cell with a set of sense voltages Vth1, Vth2, Vth3, and Vth4 to determine whether an output data value of the memory cell is 00, 01, 10, or 11. Referring to FIG. 1B, a schematic diagram of probability distribution of an output voltage of an abnormal memory cell of a multi-level cell (MLC) memory is shown. The abnormal memory cell can output four voltage levels, each voltage level corresponds to one of four storage bit combinations 00, 01, 10, and 11, and the probability distributions of the four voltage levels are respectively marked as 111, 112, 113, and 114.
In comparison with FIG. 1A, the output voltage of the abnormal memory cell is apparently lower than that of the normal memory cell. If the memory compares the output voltage of the abnormal memory cell with the original set of sense voltages Vth1, Vth2, Vth3, and Vth4 to determine whether an output data value of the abnormal memory cell is 00, 01, 10, or 11, the memory may obtain an erroneous output data value. Thus, a data read method is required to adjust the sense voltage for different memory cells to ensure accuracy of the identified output data value.